Position Name: VLSI Physical Design Trainer
Job Type: Full Time
Job Location: Dhaka, Bangladesh
Job Overview:
The trainer will be responsible for conducting hands-on training sessions on IC Physical Design (PnR). The trainer must be proficient with all relevant tools and capable of delivering theoretical and practical sessions on topics such as ASIC design flow, CMOS/DLD fundamentals, Verilog HDL, basic and complex logic gate layouts, CMOS inverter design, floorplanning, placement, clock tree synthesis, routing, physical verification (DRC/LVS), STA, LEC, IR/EM analysis, DFT, TCL scripting, and Python basics. The trainer will guide students through projects, evaluations, and final design submissions while ensuring a strong conceptual and tool-based understanding
Job Responsibilities:
•Conduct comprehensive training sessions on IC •Physical Design covering layout, PnR flow, verification, and automation
•Teach topics including ASIC design flow, semiconductor physics, CMOS/DLD, logic gate circuits, stick diagram, CMOS inverter, complex circuit layouts, floorplanning, placement, CTS, routing, STA, LEC, IR/EM analysis, DFT, TCL scripting, and Python basics
•Demonstrate hands-on use of industry-standard EDA tools including Cadence Virtuoso, IC Compiler/ICPD, Assura/Calibre LVS & DRC, Makefiles, and TCL scripting environments
•Supervise and guide trainees through project-based learning, debugging, and final layout submissions
•Prepare and evaluate theory and practical exams as per the training schedule
•Stay updated with the latest semiconductor •PnR technologies and practices
•Collaborate with other trainers and engineers to ensure consistent, high-quality training delivery
Educational Qualifications:
•B.Sc./M.Sc. in EEE, ECE, CSE, Applied Physics, or related field from a reputed university
•Completed VLSI Design or Microelectronics courses
•Strong understanding of Electronics, Solid-State Devices, CMOS/FinFET, and VLSI design flow
•IC Physical Design, layout techniques, verification, and semiconductor fabrication knowledge
•Proficient in Cadence Virtuoso, IC •Compiler/ICPD, Assura/Calibre LVS & DRC, Makefiles, TCL scripting
•Familiarity with Verilog HDL, Python, and FPGA design
Experience Requirements:
•Minimum 2 years of teaching/training experience in VLSI Physical Design, •Microelectronics, or related subjects
Industry experience in IC Physical Design, layout, or verification is highly preferred
•Hands-on experience with the tools and technologies listed above
Other Requirements:
•Excellent communication and presentation skills in English and Bangla
•Strong mentoring and teamwork abilities
Ability to manage classes, handle questions, and simplify complex topics
•Capable of working under pressure and meeting batch schedules
•Enthusiasm for guiding young engineers toward semiconductor industry readiness.
Application Deadline: 4th Dec, 2025
Application Link: https://docs.google.com/.../1qRzeNCxLQdBQxwg85wLn-Z.../edit
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